> For the complete documentation index, see [llms.txt](https://tk233.gitbook.io/notes/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://tk233.gitbook.io/notes/stm32/connectivity/ethernet/ethernet.md).

# Ethernet - LWIP

## Setting up Ethernet PHY Layer

Under "Connectivity" tab, select ETH.

Set ETH mode to RMII, and make sure the pin mapping corresponds to the one on the Nucleo board

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2FnI8dfxjlD16lIedFDsbz%2Fimage.png?alt=media&amp;token=0cb3f611-8423-4770-955a-e2e77bfd1f61" alt=""><figcaption></figcaption></figure>

{% tabs %}
{% tab title="NUCLEO-F429ZI" %}

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2Fgit-blob-3202a99c99f4852e3929038b69c4ee643030307e%2Fimage.png?alt=media" alt=""><figcaption></figcaption></figure>

On the F429ZI Nucleo board, the pin mapping should look as follows.

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2F5HnizR58azYWHG4CHaIq%2Fimage.png?alt=media&amp;token=0cfdf5de-ae6a-4772-b22a-f5975fdefc21" alt=""><figcaption></figcaption></figure>
{% endtab %}

{% tab title="NUCLEO-H755ZI" %}

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2FNsQnp4QhMY633f4qVcEL%2Fimage.png?alt=media&amp;token=5a1e810f-84ad-4514-baa0-427cefb2f97e" alt=""><figcaption></figcaption></figure>

On the H755ZI Nucleo board, the pin mapping should look as follows.

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2FXz8KcmhCFCguYcTl2ryM%2Fimage.png?alt=media&amp;token=5cd7ff41-3c50-4bcb-9af6-6e636c3dcbd5" alt=""><figcaption></figcaption></figure>
{% endtab %}
{% endtabs %}

## Setting up Middleware LWIP Protocol Layer

Under "Middleware and Software Packs" tab, select LWIP (Lightweight IP).

Enable the Lightweight IP functionality.

The Platform Settings will mark a warning icon. We will configure this at the last step.

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2FzRc5BtJABpbGZISSSEqI%2Fimage.png?alt=media&amp;token=f6bf34c6-48d9-4e89-8f9b-4a4f152d3b1e" alt=""><figcaption></figcaption></figure>

Disable DHCP and manually set the IP

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2Fgit-blob-294dce95a5c13a7af3228c993bcc142342bf7ddb%2Fimage.png?alt=media" alt=""><figcaption></figcaption></figure>

set MEM\_SIZE to 10K

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2Fgit-blob-474bbc0ed19fb062161136884ec5de0d123b5bda%2Fimage.png?alt=media" alt=""><figcaption></figcaption></figure>

Now, we configure the Platform Settings. For Nucleo 144 boards (F429, H755 etc.), we need to set to LAN8742, which corresponds to the U9 PHY IC on the board.

<figure><img src="https://1287130752-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FvVJ0h2a4qMIhB1I8GdV8%2Fuploads%2Fgit-blob-8d31e3e97b62a457bd1daed7dbf12fa427219338%2Fimage.png?alt=media" alt=""><figcaption></figcaption></figure>

```c
/* USER CODE BEGIN 0 */

extern struct netif gnetif;

/* USER CODE END 0 */

...

  /* USER CODE BEGIN WHILE */
  while (1)
  {
    /* USER CODE END WHILE */


    /* USER CODE BEGIN 3 */
    ethernetif_input(&gnetif);
  }
  /* USER CODE END 3 */

```

## Testing

After configuration, the STM32 should be able to respond to ping requests.

## Reference

{% embed url="<https://controllerstech.com/stm32-ethernet-tutorials/>" %}
