0x02. Implementation
Operation Parameters
Commutation Frequency: 20kHz
Encoder Update Frequency: 10kHz
Position Loop Update Frequency: 2kHz
Current Loop Update Frequency: 20kHz
Current Controller Bandwidth: 1kHz
Encoder Filter Bandwidth: 1kHz
1. Clock Setting
We use a 160 MHz system clock. This can be achieved by the following PLL setting
2. Pinout
3. TIM Settings
We use TIM1 to generate PWM signals for the gate driver and the trigger to ADC for current sampling.
We use TIM2 as a system timer for position loop scheduling.
We use TIM4 as a time tracking timer for the magnetic encoder, or input capture control when using the ABI incremental encoder.
3.1 TIM1 Settings
We configure Channel 1-3 to be the PWM output for the gate driver. CHx will drive the high-side of the bridge, while CHxN will drive the low-side.
Channel 4 is used to generate the trigger signal to ADC to start sample the current. Another possible way to do this is to use the timer update event. However, using the Channel 4 PWM enables control over the exact current sample point along the PWM cycle.
3.1.1 TIM1 Counter Settings and TRGO Parameters
Prescaler
is set to 0, which results in a clock value of 160 MHz / (0 + 1) = 160 MHz.
Counter Mode
is set to center-aligned mode, to generate a center-aligned PWM signal. Mode 1-3 does not matter here, as we are not using output compare functionality.
Dithering
is kept at the default value.
Counter Period (ARR)
is set to 3999, which results in a PWM frequency of 160 MHz / (3999+1) / 2 = 20 kHz
Internal Clock Division
is kept at the default value.
Repetition Counter
is set to 1 to generate an update interrupt every two counter updates. Because we are setting this before the timer is started, the update interrupt will be generated on counter underflow.
We use this to trigger the current loop calculation on the appropriate frequency and time, where the ADC just finished sampling the phase currents on the previous counter overflow.
ARR reload preload
is kept at the default value.
Master / Slave Mode
is kept at the default value.
TRGO
is set to OC4REF, where
OC4REF = OC4_pulse_value > counter_value;
TRGO2
is kept at the default value.
3.1.2 TIM1 Break and Dead Time Management - Output Configuration
Dead Time
is set to 128, which
3.1.3 TIM1 PWM Generation Channel 1-3 and 1-3N
Mode
is set to PWM mode 1
3.1.4 TIM1 PWM Generation Channel 4
Mode
is set to PWM mode 1
TIM2
TIM3
4. Analog Settings
OpAmpX Settings
OpAmp 2 and 3 are with same settings.
ADC 1
Overrun Behavior
is set to overrun data overwritten
External Trigger Source
is set to Timer 1 Trigger event
External Trigger Conversion Edge
is set to on the rising edge, which means we will start the ADC sample right before the timer counter overflow, and thus the sample point will span across the counter overflow, which then gives us the maximum sample time.
Because we need to sample multiple data at the same trigger edge for one ADC, we use the injected conversion feature of the ADC. It will sample the configured channel at trigger edge at the same time, and then convert the reading sequentially in the order of the rank number of the channels. Finally, it will store the converted data inside the ADC injected data register, which means we do not need to use interrupt or DMA to read it out before converting next channel. The data will always be available until the next sample cycle starts.
ADC2
6. CAN
7. UART
NVIC
SPI Settings
Future Iteration:
add protection on each motor controller board/
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