MIT Motor Controller Code Analyze

Clock Tree

NVIC Settings

NVIC priority is configured in the code

PowerStage PWM Generation

Using DIV/1 prescaler, 0x8CA (2250) period, and center aligned mode -> PWM frequency is 80kHz

With the repetition counter set to 1, the software interrupt frequency is 40kHz.

It handles the motor phase inversion at the last stage, before issuing value to TIM.

Current Sampling

It's using 2 phase current shunt, and using blocking ADC call to sample current.

Encoder

It's using blocking encoder read/write.

Using this line to fence off too-fast CS pin control:

This shouldn't be necessary when using blocking SPI transaction mode...

The Commutation Loop

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