> For the complete documentation index, see [llms.txt](https://tk233.gitbook.io/notes/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://tk233.gitbook.io/notes/risc-v-soc/vivado-stuff/arty-35t-100t-uart-pins.md).

# Arty 35T / 100T UART Pins

From the [official constraint file](https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-35-Master.xdc), the UART interface is labeled `uart_rxd_out` and `uart_txd_in`

![](/files/BdFD82NeiEemZiTaujXc)

Note that here, Diligent is labeling the rxd / txd pair with respect to the USB adapter IC, and in / out direction with respect to the DUT (Arty FPGA chip itself).

Thus, `uart_rxd_out` correspond to DUT's TX, while `uart_txd_in` correspond to DUT's RX pin.

As a quick reference, the `z1top.v` should use the following port definition:

```verilog
module z1top #(
  // ...
) (
  input         CLK100MHZ,
  input         ck_rst,
  
  output        uart_rxd_out,
  input         uart_txd_in,
  // ...
i);
```